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s1d16700 rev.1.1
C i C contents 1. description .................................................................................................................. .............................4-1 2. features ..................................................................................................................... ............................... 4-1 3. block diagram ................................................................................................................ ......................... 4-2 4. pin description .............................................................................................................. .......................... 4-3 5. pad .......................................................................................................................... ......................................4-4 6. functional description ....................................................................................................... ................ 4-6 7. timing chart (S1D16700D01B * ) .............................................................................................................. 4-7 8. absolute maximum ratings ..................................................................................................... ............ 4-8 9. electrical characteristics ................................................................................................... ........... 4-9 10. lcd drive power ............................................................................................................. ....................... 4-12 11. connect example ............................................................................................................. ..................... 4-13 rev.1.1
s1d16700 series rev.1.1 epson 4C1 1. description the s1d16700 is a 100 output low-power resistance common (row) driver which is suitable for driving a very high capacity dotmatrix lcd panels upto a duty ratio of 1/300. it is intended to be used in conjunction with the s1d16400 or s1d16006 as a pair. since the s1d16700 is so designed to drive lcds over a wide range of voltages, and also the maximum potential v 0 of its lcd drive bias voltages is isolated from v dd to allow the lcd driving bias voltages to be externally generated optionally with a high accuracy, it can cope with a wide range of lcd panels. owing to its pad layout which can minimize its pc boards mounting space in addition to its selectable bidirectional driver output sequence and as many as 100 lcd output segments of high pressure resistance and low output impedance, it is possible to obtain the highest driver working efficiency for the 1/200 duty panel. and the s1d16700 * 01 ** can display 65 x 132 panel when used as a common driver of ram buit-in driver, s1d15301. 2. features ? number of lcd drive output segments: 100 ? common output on resistance: 700 w (typ.) ? display duty ratio: 1/64 to 1/300 (reference) ? display capacity: possible to display 640 480 dots when used in combination with s1d 16400d or s1d16006d. ? selectable pin output shift direction ? no-bias display off function (s1d16700 * 01 ** ) ? instantaneous display blanking enabled by inhibit function (s1d16700 * 00 ** ) ? adjustable offset bias of lcd power to v dd level ? wide range of lcd drive voltages: C7 v to C28 v (absolute maximum rated voltage: C30 v) ? logic system power supply: C2.7 v to C5.5 v ? shipping pattern s1d16700d00a * (al pad chip) s1d16700d01a * (al pad chip) s1d16700d00b * (au bump chip) S1D16700D01B * (au bump chip) s1d16700t00a * (tcp) s1d16700t01a * (tcp) ? no radial rays countermeasure taken in designing
s1d16700 series 4C2 epson rev. 1.1 com0 com99 v1 v4 lcd driver 100 bit shift register 100 bit shift register 100 bit v0 v5 fr dio1 dio2 yscl inh in s1d16700 * 00 ** doff in s1d16700 * 01 ** shl doff inh com1 com2 v dd v ss voltage control circuit 3. block diagram
s1d16700 series rev.1.1 epson 4C3 number of pins pin name com0 to com099 dio1, dio2 yscl shl doff (inh) fr v dd , v ss v0, v1, v4, v5 i/o o i/o i i i i i power supply power supply 100 2 1 1 1 (1) 1 2 4 function lcd drive common (row) output the output changes at the ys cl falling edge. 100-bit shift register serial data input/output to be set to input or output according to the shl input the output changes at the yscl falling edge. serial data shift clock input the scanning data is shifted at the falling edge. shift direction selection and dio pin i/o control input lcd display blanking control input when low is input, the content of shift register is cleared and all common outputs become the v 0 level instantaneously (S1D16700D01B * ). lcd drive display blanking control input when low is input, the content of shift register is cleared and all common outputs become the non-select level instantaneously. common output = v 4 (when fr = low) common output = v 1 (when fr = high) (s1d16700d00b * ) lcd drive output ac converted signal input logic power supply v dd : 0 v (gnd) v ss : C5.0 v lcd drive power supply v 5 : C7 v to C28 v v dd 3 v 0 3 v 1 > v 4 3 v 5 shl com output shift direction dio1 dio2 low 0 ? 99 input output high 99 ? 0 ourput input inh for s1d16700 * 00 ** doff for s1d16700 * 01 ** total: 112 4. pin description
s1d16700 series 4C4 epson rev. 1.1 y x 112 1 36 37 57 93 56 92 (0,0) chip size ............................ 5.49mm 3.03mm chip thickness .................... 525 m m (au-bump die from) 400 m m (al-pad die from) 1) au bump specification reference values bump specific : high quarity au bump bump size : 90 m m 90 m m bump height : 17 m m ~ 28 m m 2) al pad specification reference values pad opening : 100 m m 100 m m 5. pad pad layout
s1d16700 series rev.1.1 epson 4C5 pad actual dimensions no. name x y 81 com85 -803 1357 82 86 -932 83 87 -1062 84 88 -1191 85 89 -1320 89 90 -1449 87 91 -1578 88 92 -1708 89 93 -1837 90 94 -1966 91 95 -2095 92 96 -2224 1357 93 97 -2473 1334 94 98 1201 95 99 1071 96 dio2 941 97 doff 715 (97) (inh) 98 fr 585 99 yscl 455 100 shl 325 101 v dd 185 102 v ss 46 103 v0 -112 104 v1 -252 105 v4 -391 106 v5 -531 107 dio1 -671 108 com0 -810 109 1 -941 110 2 -1071 111 3 -1201 112 4 -2473 -1334 pad actual dimensions no. name x y 41 com45 2584 -711 42 46 -581 43 47 -452 44 48 -323 45 49 -194 46 50 -65 47 51 65 48 52 194 49 53 323 50 54 452 51 55 581 52 56 711 53 57 840 54 58 969 55 59 1098 56 60 2584 1231 57 61 2298 1357 58 62 2168 59 63 2039 60 64 1910 61 65 1781 62 66 1652 63 67 1522 64 68 1393 65 69 1264 66 70 1135 67 71 1006 68 72 876 69 73 747 70 74 618 71 75 489 72 76 360 73 77 230 74 78 101 75 79 -28 76 80 -157 77 81 -286 78 82 -416 79 83 -545 80 84 -674 1357 pad actual dimensions no. name x y 1 com5 -2187 -1357 2 6 -2058 3 7 -1929 4 8 -1799 5 9 -1670 6 10 -1541 7 11 -1412 8 12 -1283 9 13 -1153 10 14 -1024 11 15 -895 12 16 -766 13 17 -637 14 18 -507 15 19 -378 16 20 -249 17 21 -120 18 22 10 19 23 139 20 24 268 21 25 397 22 26 526 23 27 656 24 28 785 25 29 914 26 30 1043 27 31 1172 28 32 1302 29 33 1431 30 34 1560 31 35 1689 32 36 1818 33 37 1948 34 38 2077 35 39 2206 36 40 2335 -1357 37 41 2584 -1231 38 42 2584 -1094 39 43 2584 -969 40 44 2584 -840 pad no. 97: inh for s1d16700 * 00 ** doff for s1d16700 * 01 ** pad center coordinates
s1d16700 series 4C6 epson rev. 1.1 contents of doff fr com output voltage shift register high v 5 high (select level) low v 0 high high v 1 (non-select low low v 4 level) low fixed to low C v 0 C (s1d16700 * 01 ** ) contents of inh fr com output voltage shift register high v 5 high (select level) low v 0 high high v 1 (non-select low low v 4 level) high v 1 (non-select low fixed to low low v 4 level) (s1d16700 * 00 ** ) 6. functional description shift register this is a bidirectional shift register to transfer common data. level shifter this is a level interface circuit used to convert the signal voltage level from the logic system level to lcd drive level. lcd driver circuit this driver outputs the lcd drive voltage. the relationship among the display blanking signal doff, contents of shift register, ac converted signal fr and common output voltage is as shown in the table below: the relationship among the display blanking signal inh, contents of the shift register, ac converted signal fr and com output voltage is as shown in the table below:
s1d16700 series rev.1.1 epson 4C7 dio1 yscl shl=low 1/200 duty fr 1 frame shift register (200 lines) dio2 o0 o1 o2 q0 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 v 0 v 1 v 4 v 5 q1 q2 dspoff 100 lines the v 1 or v 4 non-select level is output corresponding to the fr in s1d16700d00b * or inh=low, respectively. 7. timing chart (S1D16700D01B * )
s1d16700 series 4C8 epson rev. 1.1 parameter symbol rating unit supply voltage (1) v ss C7.0 to +0.3 v supply voltage (2) v 5 C30.0 to +0.3 v supply voltage (3) v 0 , v 1 , v 4 v 5 C0.3 to +0.3 v input voltage v i v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v output current (1) i o 20 ma output current (2) i ocom 20 ma operating temperature topr C40 to + 85 c storing temperature 1 tstg C65 to +150 c v dd =0v 8. absolute maximum ratings notes: 1. the voltage of v 0 , v 1 and v 4 must always satisfy the condition of v dd 3 v 0 3 v 1 3 v 4 3 v 5 . 2. floating of the logic system power during while the lcd drive system power is applied, or exceeding v ss = C2.6 v or more can cause permanent damage to the lsi. functional operation under these conditions is not implied. care should be taken to the power supply sequence especially in the system power on or off.
s1d16700 series rev.1.1 epson 4C9 unless otherwise specified, v dd = v 0 = 0v, v ss = C5.0v 10%, ta = C40 to 85 c. condition C C functional operation recommended value recommended value recommended value v ss =C2.7v to C5.5v v ss =C2.7v to C5.5v i oh =C0.3ma i oh =C0.2ma (v ss =C2.7 to C4.5v) i ol =+0.3ma i ol =+0.2ma (v ss =C2.7 to C4.5v) v ss v in 0v v ss v in 0v v 5 =C7.0 to C28.0v v ih =v dd , v il =v ss d von v 5 = =0.5v C20.0v v ss =C5.0v, v ih =vdd, v il =v ss , f yscl =12khz, frame frequency=60hz input data; h at no load every 1/200 duty other conditions are the same as v ss = C3.0 v v ss =C5.0, v,=C2.0v, v 4 =C18.0v, v 5 =C20.0v other conditions are the same as in the item of i ss1 . ta=25 c min. C5.5 C28.0 C C2.5 2/9v 5 v 5 0.2v ss v ss 0.2v ss v ss C 0.4 v ss C C C C C C C C C typ. C5.0 C C C C C C C C C C C C C C 0.70 7 5 7 C C max. C2.7 C7.0 C7.0 0 v dd 7/9v 5 0 0.8v ss 0 0.85v ss 0 v ss +0.4 2.0 5.0 25 1.40 15 10 15 8 15 unit v v v v v v v v v v v v m a m a m a k w m a m a pf pf parameter supply voltage (1) recommended operating voltage operation enable voltage supply voltage (2) supply voltage (3) supply voltage (4) high input voltage (1) low input voltage (1) high input voltage (2) low input voltage (2) high output voltage low output voltage input leakage current input/output leakage current static current output resistance average operating current consumption (1) average operating current consumption (2) input pin capacitance input/output pin capacitance symbol v ss v 5 v 5 v 0 v 1 v 4 v ih v il v iht v ilt v oh v ol i li i li/o i dds r com i ss1 i ss2 c i c i/o applicable pin v ss v 5 v 5 v 0 v 1 v 4 dio1, dio2, yscl, shl, fr doff, inh dio1, dio2 yscl, shl, doff, inh, fr dio1, dio2 v dd com0~com99 v ss v 5 yscl, shl, doff, inh, fr dio1, dio2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - when the v 1 , v 4 , v 0 or v 5 level is output 9. electrical characteristics dc characteristics
s1d16700 series 4C10 epson rev. 1.1 fr yscl t r t f t wclh t dfr v ih =0.2 v ss v il =0.8 v ss t ds t dh t ccl t wcll dio1 dio2 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 500 C ns yscl high pulsewidth t wclh C70Cns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 100 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parameter symbol condition min. max. unit input signal rise time t r CC50ns input signal fall time t f CC50ns yscl period t ccl C 1000 C ns yscl high pulsewidth t wclh C 160 C ns yscl low pulsewidth t wcll C 330 C ns data setup time t ds C 200 C ns data hold time t dh C10Cns allowable fr delay time t dfr C C500 500 ns the standard applicable to t ccl , t wclh , t wcll and t ds when v ss = C2.4 v shall be 1.3 times of that applies when v ss = C2.7v to C4.5v. ac characteristics input timing characteristics
s1d16700 series rev.1.1 epson 4C11 unless otherwise specified v ss =C5.0v 10%, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 30 300 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to (doff to com output) delay time tpd cdoff C28.0v C 3.0 m s (inh to com output) delay time tpd cinh cl=100pf (fr to com output) delay time tpd cfr C 3.0 m s unless otherwise specified v ss =C2.7v to C4.5v, ta=C40 to 85 c parament symbol condition min. max. unit (yscl - fall to dio) delay time tpd docl cl=15pf 60 600 ns (yscl - fall to com output) delay time tpd ccl v 5 =C7.0 to (doff to com output) delay time tpd cdoff C28.0v C 3.0 m s (inh to com output) delay time tpd cinh cl=100pf (fr to com output) delay time tpd cfr C 3.0 m s fr vn?.5v vn+0.5v t pddocl t pdccl t pdcfr t pdcdoff yscl v ih =0.2 v ss v il =0.8 v ss doff inh com dio1 dio2 the standard applicable at v ss = C2.4v shall be the same as that employed when v ss = C2.7v to C4.5v. output timing characteristics
s1d16700 series 4C12 epson rev. 1.1 10. lcd drive power each voltage level forming method to obtain each voltage level for lcd driving, it is the most simple to divide the resistance of potential as shown in the connection example. on the other hand, to obtain a high quality display, it is necessary to raise the accuracy and constancy of each voltage level and to set the divided resistance value as low as possible in the range of system power capacity. especially when a low-power lcd driving is required, set the divided resistance to a higher value and drive the lcd with a voltage follower by means of operational amplifier instead. in taking into consideration of a case where the operational amplifier is employed, the maximum potential level v0 for lcd driving has been isolated from the v dd pin. when the potential of v 0 lowers than that of v dd and the potential difference between the two becomes larger, however, the capacity of lcd drive output driver lowers. to avoid it, use the system with the potential difference of 0 v to 2.5 v between v 0 and v dd . when no operational amplifier is used, connect v 0 and v dd pins. note in power on/off since this lsi is high in the voltage of lcd driving system, when a high voltage is applied to the lcd driving system with the logic system power supply kept floating, an overcurrent flows and lsi breaks down in some cases. be sure to follow the power on/off sequence as shown below: at power on ... logic system on ? lcd driving system on or simultaneous on of the both at power off ... lcd driving system off ? logic system off or simultaneous off of the both
s1d16700 series rev.1.1 epson 4C13 11. connect example 200 x 640 dot matrix lcd panel seg 79 0 seg 79 0 seg 79 0 v dd eio2 1 eio1 shl eio2 2 eio1 shl eio2 8 eio1 shl 1 2 yscl shl dio1 dio2 yscl shl dio1 dio2 fr fr s1d16700d lp yd v ss v dd v 0 v 1 v 2 v 3 v 4 v 5 vssh wf xscl xd0~xd3 v ss 6 6 r r r r 11r 322 322 fr lp d0e3 xscl fr lp d0e3 xscl fr lp d0e3 xscl s1d16006d com 0 99 com 0 99 note *1 it must be provided as the protective resister against overcurrent. also, the bypass capacitor (0.01 f) for noise suppression must be provided near to v ss and v5 terminals on each lsi.

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